1. Field of the Invention
The present invention relates to a lateral planar type power semiconductor device such as a lateral planar type power metal oxide semiconductor (MOS, broadly, metal insulating semiconductor (MIS)) transistor and its manufacturing method.
2. Description of the Related Art
Power MOS transistors have been used to control high voltages and large currents. Such power MOS transistors have specific structures as compared with conventional non-power MOS transistors.
For example, a typical conventional non-power n-type MOS transistor is constructed by an n+-type source impurity diffusion region and an n+-type drain impurity diffusion region spaced in a p−-type semiconductor substrate. On the other hand, a typical power n-type MOS transistor is constructed by an n+-type source impurity diffusion region, an n+-type drain impurity diffusion region spaced from the n+-type source impurity diffusion region, and an n−-type drain drift impurity diffusion region adjacent to the n+-type drain impurity diffusion region between the two n+-type impurity diffusion regions formed in a p−-type semiconductor substrate. In this case, generally, the larger in size the n−-type drain drift impurity diffusion region, the higher the breakdown voltage. Also, the smaller the impurity concentration of the n−-type drain drift impurity diffusion region, the higher the breakdown voltage.
In order to increase the size of the above-mentioned drain drift impurity diffusion region, vertical type power MOS transistors rather than lateral type power MOS transistors are used; however, the vertical type power MOS transistors require a high manufacturing cost (see: FIG. 52 of JP-A-2001-274398).
Lateral power MOS transistors are divided into a groove type and a planar type. Since the lateral groove type power MOS transistors have deeper drain drift impurity diffusion regions, the lateral groove type power MOS transistors can be highly integrated (see: FIG. 1 of JP-A-2001-274398). However, the lateral groove type power MOS transistors require a high manufacturing cost.
While lateral planar type power MOS transistors are not so highly integrated, the lateral planar type power MOS transistors do not require a high manufacturing cost.
A prior art lateral planar type power MOS transistor is constructed by a semiconductor substrate of a first conductivity type, source and drain impurity diffusion regions of a second conductivity type spaced in a surface portion of the semiconductor substrate, a drain drift impurity diffusion region of the second conductivity type in the surface portion adjacent to the drain impurity diffusion region, and a base impurity diffusion region of the first conductivity type in the surface region adjacent to the source impurity diffusion region (see: JP-A-5-029620). This will be explained later in detail.
In the above-described prior art lateral planar type power MOS transistor, however, since carriers through a deeper stream in the drain drift impurity diffusion region have a longer motion distance than carriers through a shallow stream in the drain drift impurity diffusion region, the ON-resistance is substantially increased.